1. Field of the Invention
The present invention relates to processing of single polysilicon bipolar junction transistors, and more particularly to the use of cumulative photoresist application patterning.
2. Background Information
For a standard single polysilicon (poly) bipolar junction transistor processing flow, the emitter poly is defined using photoresist and etched using industry standard methods. The emitter definition photoresist is stripped prior to the application and patterning of the extrinsic base implant photoresist. This approach uses the already defined poly emitter (rather than non-self-aligned extrinsic base masking photoresist) to self align the extrinsic base implant to the intrinsic transistor. As a result of this, the poly emitter is doped with the extrinsic base implant. Because this implant is a lower dose than the emitter implant, it does not change the doping type of the emitter, even though it is of the opposite doping type.
FIGS. 1A and 1B show a simplified processing sequence for this prior art. FIG. 1A shows the single poly transistor emitter stack just after the emitter poly has been etched. FIG. 1B shows the same transistor during the subsequent extrinsic base implant step. This step is required to reduce the external component of the base resistance and also to later allow the formation of ohmic base contacts. Notice that the emitter poly 2 is used to block the implant 6 from the intrinsic regions of the device. This is good in that it self-aligns the intrinsic and extrinsic parts of the BJT, but bad in that the emitter poly receives the implant.
By definition, the emitter and the bases of a bipolar transistor are of different doping polarities. So, in an NPN transistor, the emitter is doped n-type (possibly with arsenic) and the base p-type (probably with boron). Therefore, during the extrinsic base implant shown in FIG. 1B, the emitter poly will be counter doped with the base doping type. During the final anneal step the unwanted p-type dopant in the emitter poly is driven into the single crystal silicon below along with the intended emitter dopant. This contamination reduces the transistor current gain (beta) by lowering the resultant emitter doping at the base-emitter junction. Other transistor characteristics are also negatively impacted. To some extent, these effects can be mitigated by good device engineering, but they can never be entirely eliminated.
Even if device adjustments are made for the unwanted dopant in the emitter polysilicon, this prior art self-alignment method has other limitations. The most obvious is a constraint on the minimum emitter poly thickness, since this layer must be at least thick enough to block the extrinsic base implant. Without this constraint, the device design might choose to make the emitter poly thinner to better optimize the transistor.
The present invention is directed to the above and other limitations of the prior art.